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Multicycle Path Constraints Parameters

This section contains parameters in the Multicycle Path Constraints section of the HDL Code Generation > Optimization pane of the Configuration Parameters dialog box.

Synthesis tools require that data propagates from a source register to a destination register within one clock cycle. However, multicycle paths cannot complete their execution within one clock cycle and therefore cannot meet the timing requirements. To meet the timing requirement of multicycle paths, use the parameters in this section to generate a register-to-register path information file or to generate enable-based constraints that uses the timing controller enable signals.

Enable based constraints

To meet the timing requirement of multicycle paths in your Simulink® design in single clock mode, use enable-based constraints. Enable-based constraints relax the timing requirement by allowing multiple clock cycles for data to propagate between the registers. The constraints use the timing controller enable signals to create enable-based register groups, with registers in each group driven by the same clock enable.

Settings

Default: Off

On

When you enable this setting and generate HDL code, HDL Coder™ generates a constraints file with the naming convention dutname_constraints. The format of the file name depends on the synthesis tool that you specify. The constraints file defines the timing requirements of multicycle paths and contains information about the clock multiples for calculating the setup and hold time information.

Off

Do not generate a multicycle path constraints file.

Dependency

If you select the Enable based constraints check box, make sure that you clear the Clock-rate pipelining check box. Using enable-based multicycle path constraints is an alternative to the clock-rate pipelining optimization. You can clear the Clock-rate pipelining check box in the HDL Code Generation > Target > Pipelining tab.

Command-Line Information

Parameter: MulticyclePathConstraints
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can enable the MulticyclePathConstraints setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'MulticyclePathConstraints','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','MulticyclePathConstraints','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Register-to-register path info

Generate a text file that reports multicycle path constraint information. The text file describes one or more multicycle path constraints that is agnostic to the synthesis tool. You must convert this information to the format required by the synthesis tool. It is recommended that you use the enable-based constraints setting instead to meet the timing requirements of multicycle paths. When you use that setting, the generated constraints are more robust to name changes in synthesis tools, and are supported with Xilinx Vivado, Xilinx ISE, and Altera Quartus II.

Settings

Default: Off

On

Generate a text file that reports multicycle path constraint information, for use with synthesis tools.

The file name for the multicycle path information file derives from the name of the DUT and the postfix '_constraints', as follows:

DUTname_constraints.txt

For example, if the DUT name is symmetric_fir, the name of the multicycle path information file is symmetric_fir_constraints.txt.

Off

Do not generate a multicycle path information file.

Command-Line Information

Parameter: MulticyclePathInfo
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can enable the MulticyclePathInfo setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'MulticyclePathInfo','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','MulticyclePathInfo','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also