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FPGA Floating-Point Library Targeting Parameters

This section contains parameters in the HDL Code Generation > Floating Point pane of the Configuration Parameters dialog box. Use these parameters to specify the latency strategy, objective, and whether to initialize the pipeline registers in the floating-point target IP to zero.

Initialize IP Pipelines To Zero

Inserts additional logic during HDL code generation to initialize the values of pipeline registers in the Altera® floating-point target IP to zero. If you do not select this check box, HDL Coder™ reports a warning during HDL code generation.

Settings

Default: On

On

Inserts additional logic to initialize pipeline registers in the floating-point target IP to zero.

Off

Does not add additional logic to initialize pipeline registers in the floating-point target IP to zero.

Dependency

To specify this parameter, set the Floating Point IP Library to Altera Megafunctions (ALTERA FP FUNCTIONS). Before you set the floating-point library, specify the path to your synthesis tool by using the hdlsetuptoolpath function.

Command-Line Information

To specify this setting:

  1. Create a floating-point target configuration object with Altera Megafunctions (ALTERA FP FUNCTIONS) as the floating-point target library.

    fpconfig = hdlcoder.createFloatingPointTargetConfig('AlteraFPFunctions');

  2. Specify the InitializeIPPipelinesToZero property of the LibrarySettings attribute of the floating-point target configuration object.

    fpconfig.LibrarySettings.InitializeIPPipelinesToZero = 0;

  3. Set the floating-point target configuration on the model and then generate HDL code. This example shows how to set the configuration on the sfir_single model and generate HDL code for the symmetric_fir subsystem:

    hdlset_param('sfir_single','FloatingPointTargetConfig',fpconfig)
    makehdl('sfir_single/symmetric_fir')

See Also

Latency Strategy

Specify whether you want the design to map to minimum or maximum latency with Xilinx® LogiCORE or ALTFP Altera megafunction IPs.

Settings

Default: MIN

The options are:

MIN

Maps to minimum latency for the specified floating-point target IP.

MAX

Maps to maximum latency for the specified floating-point target IP.

Dependency

To specify this parameter, set the Floating Point IP Library to Altera Megafunctions (ALTFP) or Xilinx LogiCORE. Before you set the floating-point library, specify the path to your synthesis tool by using the hdlsetuptoolpath function.

Command-Line Information

To specify this setting:

  1. Create a floating-point target configuration object with Altera Megafunctions (ALTERA FP FUNCTIONS) as the floating-point target library.

    fpconfig = hdlcoder.createFloatingPointTargetConfig('ALTFP');

  2. Specify the LatencyStrategy property of the LibrarySettings attribute of the floating-point target configuration object.

    fpconfig.LibrarySettings.LatencyStrategy = 'MAX';

  3. Set the floating-point target configuration on the model and then generate HDL code. This example shows how to set the configuration on the sfir_single model and generate HDL code for the symmetric_fir subsystem:

    hdlset_param('sfir_single','FloatingPointTargetConfig',fpconfig)
    makehdl('sfir_single/symmetric_fir')

See also

Objective

Specify whether you want to optimize the design for speed or area when mapping to floating-point target libraries.

Settings

Default: SPEED

The options are:

NONE

Select this option if you do not want to optimize the design for speed or area.

SPEED

Select this option to optimize the design for speed.

AREA

Select this option to optimize the design for area.

Dependency

To specify this parameter, set the Floating Point IP Library to Altera Megafunctions (ALTFP) or Xilinx LogiCORE. Before you set the floating-point library, specify the path to your synthesis tool by using the hdlsetuptoolpath function.

Command-Line Information

To specify this setting:

  1. Create a floating-point target configuration object with Altera Megafunctions (ALTERA FP FUNCTIONS) as the floating-point target library.

    fpconfig = hdlcoder.createFloatingPointTargetConfig('ALTFP');

  2. Specify the Objective property of the LibrarySettings attribute of the floating-point target configuration object.

    fpconfig.LibrarySettings.Objective = 'AREA';

  3. Set the floating-point target configuration on the model and then generate HDL code. This example shows how to set the configuration on the sfir_single model and generate HDL code for the symmetric_fir subsystem:

    hdlset_param('sfir_single','FloatingPointTargetConfig',fpconfig)
    makehdl('sfir_single/symmetric_fir')

See also

IP Settings

The IP Settings section has an IP configuration table with the IP names and data types and additional options to specify a custom latency and any extra arguments.

The options in the IP configuration table depend on the library that you specify.

  • If you specify the ALTERA MEGAFUNCTION (ALTERA FP FUNCTIONS) library, HDL Coder infers the latency value from the Target Frequency (MHz) value.

  • If you specify the ALTERA MEGAFUNCTION (ALTFP) or XILINX LOGICORE libraries, HDL Coder infers the IP latency from the Latency Strategy setting. The IP configuration table has two additional columns, MinLatency and MaxLatency, that contain the minimum and maximum latency values for each IP in the table.

The IP configuration table has these sections:

  • Name: Contains a list of IP names that HDL Coder map the Simulink® blocks to, such as ABS, ADDSUB, and CONVERT.

  • DataType: Contains a list of IP data types for each IP in the table. These are mostly SINGLE and DOUBLE data types. The CONVERT IP blocks can have DOUBLE_TO_NUMERICTYPE, NUMERICTYPE_TO_DOUBLE data types, and so on.

  • Latency: The default latency value of –1 means that the IP inherits the latency value from the target frequency or the latency strategy setting depending on the library that you choose. To customize the latency of the IP that your Simulink blocks map to, enter your own custom value for the latency.

  • ExtraArgs: Specify any additional settings that is specific to the IP.

For example, if you have an Add block with Single data types in your Simulink model, HDL Coder maps the block to the ADDSUB IP. If you want to specify a custom latency value, say 8, for the IP, enter the value in the Latency column for the IP.

cmultusage is a parameter that you can specify with the Xilinx LogiCORE® libraries.

Dependency

To specify this parameter, set the Floating Point IP Library to Altera Megafunctions (ALTFP) or Xilinx LogiCORE. Before you set the floating-point library, specify the path to your synthesis tool by using the hdlsetuptoolpath function.

Command-Line Information

To specify this setting:

  1. Create a floating-point target configuration object with Altera Megafunctions (ALTERA FP FUNCTIONS) as the floating-point target library.

    fpconfig = hdlcoder.createFloatingPointTargetConfig('ALTFP');

  2. To view the floating-point IP configuration, use the IPConfig object.

    fpconfig.IPConfig

  3. To customize the latency or specify additional arguments, use the customize method.

    fpconfig.IPConfig.customize('ADDSUB','Single','Latency',6);

  4. Set the floating-point target configuration on the model and then generate HDL code. This example shows how to set the configuration on the sfir_single model and generate HDL code for the symmetric_fir subsystem:

    hdlset_param('sfir_single','FloatingPointTargetConfig',fpconfig)
    makehdl('sfir_single/symmetric_fir')

See also