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Compilation Script Parameters

This page describes configuration parameters that reside in the HDL Code Generation > EDA Tool Scripts > Compilation Script tab of the Configuration Parameters dialog box.

Compile file postfix

Specify a postfix to append to the DUT or test bench name to form the compilation script file name.

Settings

Default: _compile.do

For example, if the name of the device under test or test bench is my_design, HDL Coder™ adds the postfix _compile.do to form the name my_design_compile.do.

Command-Line Information

Property: HDLCompileFilePostfix
Type: character vector
Default: '_compile.do'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

Compile initialization

Format name passed to fprintf to write the Init section of the compilation script.

Settings

Default: vlib %s\n

The Init phase of the script performs required setup actions, such as creating a design library or a project file.

The implicit argument, %s, is the contents of the 'VHDLLibraryName' property, which defaults to'work'. You can override the default Init string ('vlib work\n' by changing the value of 'VHDLLibraryName'.

Command-Line Information

Property: HDLCompileInit
Type: character vector
Default: 'vlib %s\n'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

Compile command for VHDL

Format name passed to fprintf to write the Cmd section of the compilation script for VHDL® files.

Settings

Default: vcom %s %s\n

The command-per-file phase (Cmd) of the script is called iteratively, once per generated HDL file. On each call, a different file name is passed in.

The two implicit arguments in the compile command are the contents of the SimulatorFlags property and the file name of the current entity or module. To omit the flags, set SimulatorFlags to '' (the default).

Command-Line Information

Property: HDLCompileVHDLCmd
Type: character vector
Default: 'vcom %s %s\n'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

Compile command for Verilog

Format name passed to fprintf to write the Cmd section of the compilation script for Verilog® files.

Settings

Default: vlog %s %s\n

The command-per-file phase (Cmd) of the script is called iteratively, once per generated HDL file. On each call, a different file name is passed in.

The two implicit arguments in the compile command are the contents of the SimulatorFlags property and the file name of the current entity or module. To omit the flags, set SimulatorFlags property to '' (the default).

Command-Line Information

Property: HDLCompileVerilogCmd
Type: character vector
Default: 'vlog %s %s\n'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

Compile termination

Format name passed to fprintf to write the termination portion of the compilation script.

Settings

Default: empty character vector

The termination phase (Term) is the final execution phase of the script. One application of this phase is to execute a simulation of HDL code that was compiled in the Cmd phase. The Term phase does not take arguments.

Command-Line Information

Property: HDLCompileTerm
Type: character vector
Default: ''

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also