By using the
IP Core Generation workflow in the HDL Workflow Advisor,
HDL Coder™ can generate an IP core that contains the HDL source code and the C header
files for integrating the IP core into your EDK project, and then program the target
Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.
You generate an HTML custom IP core report by default when you generate a custom IP core.
Learn various example designs that use multiple sample rates with IP Core Generation workflow.
When you open the HDL Workflow Advisor and run the
IP Core Generation
workflow for your Simulink® model, you can specify a generic Xilinx platform or a generic Intel platform.
Board-independent IP core generation from MATLAB®.
Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces.
In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you:The following synchronization modes are available:
Learn how HDL Coder automatically inserts logic to synchronize global reset signal to IP core clock domain.
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.