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Custom IP Core Generation

Generate an HDL IP core that contains HDL code for deployment on standalone FPGA boards, Speedgoat boards, Xilinx® Zynq®-7000 platform, or Intel® SoC Devices

By using the IP Core Generation workflow in the HDL Workflow Advisor, HDL Coder™ can generate an IP core that contains the HDL source code and the C header files for integrating the IP core into your EDK project, and then program the target hardware.


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hdlcoder.BoardBoard registration object that describes SoC custom board
hdlcoder.WorkflowConfigConfigure HDL code generation and deployment workflows
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design


IP Core Generation

Custom IP Core Generation

Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.

Custom IP Core Report

You generate an HTML custom IP core report by default when you generate a custom IP core.

Multirate IP Core Generation

Learn various example designs that use multiple sample rates with IP Core Generation workflow.

Generate Board-Independent HDL IP Core from Simulink Model

When you open the HDL Workflow Advisor and run the IP Core Generation workflow for your Simulink® model, you can specify a generic Xilinx platform or a generic Intel platform.

Generate Board-Independent IP Core from MATLAB Algorithm

Board-independent IP core generation from MATLAB®.

Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces

Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces.

Processor Synchronization and IP Caching

Processor and FPGA Synchronization

In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you:The following synchronization modes are available:

Synchronization of Global Reset Signal to IP Core Clock Domain

Learn how HDL Coder automatically inserts logic to synchronize global reset signal to IP core clock domain.

IP Caching for Faster Reference Design Synthesis

Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.


Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples