Hardware Targeting Basics

Learn the basics of targeting FPGA and SoC platforms

When you target hardware by using HDL Coder™, you can follow one workflow with two different starting points, depending on your goal:

To rapidly prototype an off the shelf, pre-existing hardware platform, prototype and deploy your HDL algorithm for your FPGA using a pre-existing board and reference design and start the Hardware-Software Co-Design workflow.
For a production workflow that targets a custom device, create a custom hardware platform. Then follow the Hardware-Software Co-Design workflow.

For more details, see Targeting FPGA & SoC Hardware Overview and Hardware-Software Co-Design Workflow for SoC Platforms.

Classes

hdlcoder.WorkflowConfig Configure HDL code generation and deployment workflows

Topics

Targeting FPGA & SoC Hardware Overview
High-level steps for targeting an FPGA or SoC platform.
Hardware-Software Co-Design Workflow for SoC Platforms
High-level workflow steps for targeting an SoC platform.
Getting Started with the HDL Workflow Advisor
Learn the basics of the HDL Workflow Advisor and how to run various tasks.
Run HDL Workflow with a Script
Export, import, or configure an HDL Workflow CLI command script.
Workflows in HDL Workflow Advisor
Learn about the HDL Workflow Advisor and various workflows you can choose and platforms you can target.
Get Started with HDL Workflow Command-Line Interface
Use the HDL Workflow Advisor to run HDL workflows from the command line and the Export to Script option.
Generate IP Core from MATLAB for Blinking LED on FPGA Board
This example shows how to use the MATLAB® HDL Workflow Advisor to generate a custom HDL IP core that blinks LEDs on an FPGA board.

Featured Examples

Getting Started with Targeting Xilinx Zynq Platform

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® ZC702 evaluation kit.

Open Script

Getting Started with Targeting Zynq UltraScale+ MPSoC Platform

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® UltraScale+ MPSoC.

Open Script

Getting Started with Targeting Intel SoC Devices

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Arrow® SoCKit® evaluation kit.

Open Script

Getting Started with Targeting Intel Quartus Pro Based Devices

Define and register the board and reference design for the Intel® Arria10 SoC development kit. In this example, you use a partitioned hardware-software co-design implementation to blink LEDs at various frequencies. In this example, you register the Arria 10 SoC development kit and the reference design in the HDL Workflow Advisor. The reference design also shows the *Early I/O (Split bitstream)* feature supported by Intel Arria 10 SoC in HDL Workflow Advisor. This example uses Embedded Coder(R) to generate C code that runs on the ARM(R) processor to control the LED blink frequency. You can prepare your design for hardware and software implementation on the Intel Arria 10 SoC by deciding which system elements are performed by the programmable logic, and which system elements will run on the ARM Cortex-A9.

Open Live Script

Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Xilinx® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Xilinx JTAG AXI Master to access the DUT registers using Vivado® Tcl console by writing Tcl commands. For the Xilinx JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Xilinx Kintex®-7 KC705 board.

Open Script

Access DUT Registers on Intel Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Intel® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Intel Qsys JTAG to Avalon® Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys system console. For the Intel JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Arrow® DECA MAX® 10 FPGA evaluation kit.

Integrate HDL IP Core with Microchip PolarFire SoC Icicle Kit Reference Design

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Microchip PolarFire SoC Icicle kit.

Open Script

Getting Started with Targeting Xilinx Versal ACAP Platform

Use HDL Coder™ and the hardware-software codesign workflow to blink LEDs at various frequencies on the Xilinx® Versal® ACAP platform.

Open Script