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Custom Reference Design

Create your own custom reference design for integrating the generated IP core into the target SoC device, Speedgoat® I/O modules, or the standalone FPGA boards

You can create your own custom reference design in MATLAB® and use HDL Coder™ to integrate the IP core into your reference design.

Classes

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hdlcoder.BoardBoard registration object that describes SoC custom board
hdlcoder.WorkflowConfigConfigure HDL code generation and deployment workflows
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design

Functions

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socExportReferenceDesignExport custom reference design for HDL Workflow Advisor
addExternalIOInterfaceDefine external IO interface for board object
addExternalPortInterfaceDefine external port interface for board object
addInternalIOInterfaceAdd and define internal IO interface between generated IP core and existing IP cores
addAXI4MasterInterfaceAdd and define AXI4 Master interface
addAXI4SlaveInterfaceAdd and define AXI4 slave interface
addAXI4StreamInterfaceAdd AXI4-Stream interface
addAXI4StreamVideoInterfaceAdd AXI4-Stream Video interface
addClockInterfaceAdd clock and reset interface
addCustomEDKDesignSpecify Xilinx EDK MHS project file
addCustomQsysDesignSpecify Altera Qsys project file
addCustomVivadoDesignSpecify Xilinx Vivado exported block design Tcl file
addIPRepositoryInclude IP modules from your IP repository folder in your custom reference design
addParameterAdd and define custom parameters for your reference design
validateReferenceDesignCheck property values in reference design object
validateBoardCheck property values in board object
CallbackCustomProgrammingMethodFunction handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
CustomizeReferenceDesignFcnFunction handle for callback function that gets executed before Set Target Interface task in the HDL Workflow Advisor
EmbeddedCoderSupportPackageSpecify whether to use an Embedded Coder support package
PostBuildBitstreamFcnFunction handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
PostCreateProjectFcnFunction handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
PostSWInterfaceFcnFunction handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
PostTargetInterfaceFcnFunction handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
PostTargetReferenceDesignFcnFunction handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor

Topics

Board and Reference Design Registration System

System for defining and registering boards and reference designs.

Register a Custom Board

Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.

Register a Custom Reference Design

Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.

Define Custom Parameters and Callback Functions for Custom Reference Design

Learn how to define custom parameters and custom callback functions for your custom reference design.

Customize Reference Design Dynamically Based on Reference Design Parameters

Learn how to customize the reference design dynamically by using the CustomizeReferenceDesignFcn method.

Define and Add IP Repository to Custom Reference Design

Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.

Define Multiple AXI Master Interfaces in Reference Designs to access DUT AXI4 Slave Interface

Learn how you can specify multiple AXI Master interfaces in the custom reference design to access HDL DUT IP AXI4 slave interface.

Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces

Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces.

Export Custom Reference Design from SoC Model (SoC Blockset)

Use the socExportReferenceDesign function to export a custom reference design from an SoC Blockset™ model.

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples