Custom IP Core Generation

Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board

HDL Coder™ can generate a custom HDL IP core that you can deploy to the devices. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you register for the board.

Topics

Generate an IP Core for Zynq Platform from MATLAB
IP core generation for Zynq^® platform from MATLAB^®.
Generate an IP Core for Zynq Platform from Simulink
IP core generation for Zynq platform from Simulink^®.
Custom IP Core Generation
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor.
Custom IP Core Report
You generate an HTML custom IP core report by default when you generate a custom IP core.
IP Caching for Faster Reference Design Synthesis
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples

Save Target Hardware Settings in Model

Save your target hardware settings in a Simulink® model.

Open Script

IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip

Illustrates how to model an I2C controller using an I2C Master controller modeled using Stateflow® blocks for configuring the audio codec chip.

Open Script