Generate real or complex sinusoidal signals—optimized for HDL code generation
DSP System Toolbox HDL Support / Signal Operations
DSP System Toolbox HDL Support / Sources
The NCO HDL Optimized block generates real or complex sinusoidal signals, while providing hardwarefriendly control signals. The block uses the same phase accumulation and lookup table algorithm as implemented in the NCO block. When you use integer or fixedpoint input signals, or use the block as a source with no input signal, the block uses quantized integer accumulation to create a sinusoid signal.
The NCO HDL Optimized block provides these features:
A lookup table compression option to reduce the lookup table size. This compression results in less than one LSB loss in precision. See Lookup Table Compression for more information.
An option to synthesize the lookup table to a ROM when using HDL Coder™ with an FPGA target. To enable this feature, rightclick the
block, select HDL Code > HDL Block Properties, and set LUTRegisterResetType
to none
.
An optional input port for external dither.
An optional reset port that triggers a reset of the phase to its initial value during the sinusoid output generation.
An optional output port for the current NCO phase.
Given a desired output frequency F_{0}, calculate the phase increment input value using
$$phaseincrement=(\frac{{F}_{0}\cdot {2}^{N}}{{F}_{s}})$$
, where N is the accumulator word length and
$${F}_{s}=\frac{1}{{T}_{s}}=\frac{1}{sampletime}$$
You can specify the phase increment using a parameter or an input port.
The frequency resolution of an NCO is defined by
$$\Delta f=\frac{1}{{T}_{s}\cdot {2}^{N}}\text{Hz}$$
Given a desired phase offset (in radians), calculate the phase offset input value using
$$phaseoffset=\frac{{2}^{N}\cdot desiredphaseoffset}{2\pi}$$
You can specify the phase offset using a parameter or an input port.
When you use floatingpoint input signals, the block does not quantize the accumulation. Therefore, you must choose increment and offset values to represent a fraction of 2π without quantization, see Compute FloatingPoint Phase Increment for NCO HDL Optimized.
This block appears in the Sources libraries with
Phase increment source parameter set to
Property
. The only input port is
validIn.
This block appears in the Signal Operations libraries
with Phase increment source parameter set to
Input port
. This configuration shows the
optional input port inc.
This icon shows the optional ports of the NCO HDL Optimized block.
inc
— Phase increment (optional)Phase increment, specified as a scalar integer. If the increment is a
fixedpoint value, the block uses only the integer bits and ignores any
fractional bits. double
and single
data types are supported for simulation but not for HDL code generation.
When you use floatingpoint input signals, you must choose increment and
offset values to represent a fraction of 2π, see Compute FloatingPoint Phase Increment for NCO HDL Optimized.
To enable this port, set Phase increment
source to Input
port
.
Data Types: single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixdt([],N,0)
offset
— Phase offset (optional)Phase offset, specified as a scalar integer. If the offset is a
fixedpoint value, the block uses only the integer bits and ignores any
fractional bits. double
and single
data types are supported for simulation but not for HDL code generation.
When you use floatingpoint input signals, you must choose increment and
offset values to represent a fraction of 2π, see Compute FloatingPoint Phase Increment for NCO HDL Optimized.
To enable this port, set Phase offset source
to Input port
.
Data Types: single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixdt([],N,0)
dither
— Dither (optional)Dither, specified as a scalar integer. double
and
single
data types are supported for simulation
but not for HDL code generation.
To enable this port, set Dither source to
Input port
.
Data Types: single
 double
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixdt([],N,0)
reset
— Reset accumulator (optional)true
 false
Control signal that resets the accumulator, specified as a scalar
boolean. When this signal is true
(1
), the block resets the accumulator to 0.
To enable this port, select Enable reset input port.
Data Types: Boolean
validIn
— Enable signal (optional)true
 false
Control signal that enables NCO operation. When this signal is
true
(1
), the block increments
the phase. When this signal is false
(0
), the block holds the phase.
To enable this port, select Enable valid input port.
Data Types: Boolean
sin, cos, exp
— Generated waveformGenerated waveform, returned as a scalar sin or
cos value, as a scalar exp
value representing sine + j*cosine
, or as two values,
sin and cos. If any input
is floatingpoint type, the block returns floatingpoint values,
otherwise the block returns fixedpoint values. Floating point types are
supported for simulation but not for HDL code generation.
By default, this output port is a sine wave, sin. The port label and format changes based on your selection for Type of output signal.
phase
— Current phase of NCO (optional)Current phase of NCO, returned as a scalar of type
fixdt(1,M,Z)
, where M
is the
number of quantized accumulator bits, and Z
is the
accumulator word length. The block returns phase as
floating point if the input to the block is a floating point.
Floatingpoint types are supported for simulation but not for HDL code
generation.
To enable this port, select Enable phase port.
Data Types: single
 double
 fixdt(1,NumQuantizerAccumulatorBits,AccumulatorWL)
validOut
— Indicates valid output data true
 false
Control signal that indicates whether the other output port values are
valid or not. When validOut is
true
(1
), the values on the
sin, cos,
exp, and phase ports are
valid. When validOut is false
(0
), the values on the output ports are not
valid.
Data Types: Boolean
This block supports double
and single
input for simulation but not for HDL code generation. When an input is fixed
point, or when all input ports are disabled, the block computes the output
waveform based on the fixedpoint mask settings. When an input is floating
point, the block computes a doubleprecision output waveform and ignores
parameters related to fixedpoint settings (Number of dither
bits, Quantize phase, Number of
quantizer accumulator bits, Enable look up table
compression method, and the Data Types
tab).
To use the data type override feature of FixedPoint
Designer™, you can obtain a double
output value by
applying double
input data to one of the optional ports. When
you switch to using a floatingpoint phase increment, you must adjust the value
of the increment to account for the lack of phase quantization. See Compute FloatingPoint Phase Increment for NCO HDL Optimized.
Phase increment source
— Source of phase incrementInput port
(default)  Property
You can set the phase increment with an input port or by entering a
value for the parameter. If you select
Property
, the Phase
increment parameter appears for you to enter a value. If
you select Input port
, the
inc port appears on the block.
Phase increment
— Phase increment for generated waveform100
(default)  scalar integerPhase increment for the generated the waveform, specified as a scalar
integer. If the increment is a fixedpoint value, the block uses only
the integer bits and ignores any fractional bits.
double
and single
data types
are supported for simulation but not for HDL code generation. When you
use floatingpoint input signals, you must choose increment and offset
values to represent a fraction of 2π, see Compute FloatingPoint Phase Increment for NCO HDL Optimized.
This parameter is visible when you set Phase increment
source to Property
.
Data Types: single
 double
 int8
 int16
 int32
 uint8
 uint16
 uint32
 fixdt([],N,0)
Phase offset source
— Source of phase offsetInput port
(default)  Property
You can set the phase offset with an input port or by entering a value
for the parameter. If you select Property
,
the Phase offset parameter appears for you to enter
a value. If you select Input port
, the
offset port appears on the block.
Phase offset
— Phase offset for generated waveform0
(default)  scalar integerPhase offset for the generated waveform, specified as a scalar
integer. If the increment is a fixedpoint value, the block uses only
the integer bits and ignores any fractional bits.
double
and single
data types
are supported for simulation but not for HDL code generation. When you
use floatingpoint input signals, you must choose increment and offset
values to represent a fraction of 2π, see Compute FloatingPoint Phase Increment for NCO HDL Optimized.
This parameter is visible when you set Phase offset
source to Property
.
Data Types: single
 double
 int8
 int16
 int32
 uint8
 uint16
 uint32
 fixdt([],N,0)
Dither source
— Source of number of dither bitsProperty
(default)  Input port
 None
You can set the dither from an input port or from a parameter. If you
select Property
, the Number of
dither bits parameter appears. If you select
Input port
, a port appears on the block.
If you select None
, the block does not add
dither.
Number of dither bits
— Bits used to express dither4
(default)  positive integerNumber of dither bits, specified as a positive integer.
This parameter is visible when you set Dither
source to Property
.
Quantize phase
— Quantize accumulated phaseWhen this parameter is enabled, the block quantizes the result of the phase accumulator to a fixed bitwidth. This quantized value is used to select a waveform value from the lookup table. Select the resolution of the lookup table using the Number of quantizer accumulator bits parameter.
The frequency resolution of an NCO is defined by
$$\Delta f=\frac{1}{{T}_{s}\cdot {2}^{N}}\text{Hz}$$
When you disable this parameter, the block uses the full accumulator data type as the address of the lookup table.
Number of quantizer accumulator bits
— Bits used to express phase12
(default)  integerNumber of quantizer accumulator bits, specified as an integer scalar greater than 1 and less than the accumulator word length. This parameter must be less than or equal to 17 bits for HDL code generation. The lookup table of sine values has 2^{NumQuantizerAccumBits2} entries.
This parameter is visible when you select Quantize phase.
Enable look up table compression method
— Compress the lookup tableBy default, the block implements a noncompressed lookup table, and the output of this block matches the output of the NCO block. When you enable this option, the block implements a compressed lookup table. The Sunderland compression method reduces the size of the lookup table, losing less than one LSB of precision. The spurious free dynamic range (SFDR) is empirically 1–3 dB lower than the noncompressed case. The hardware savings of the compressed lookup table allow room to improve performance by increasing the word length of the accumulator and the number of quantize bits. For detail of the compression method, see Algorithms.
Enable reset input port
— Enable reset control signalWhen selected, the reset port appears on the
block. When reset is true
(1
), the block resets the accumulator to
zero.
Enable valid input port
— Enable valid control signalWhen selected, the validIn port appears on the
block. When validIn is true
(1
), the block increments the phase. When
validIn is false
(0
), the phase is held.
Type of output signal
— Format of output waveformSine
(default)  Cosine
 Complex exponential
 Sine and cosine
If you select Sine
or
Cosine
, the block shows the applicable
port, sin or cos. If you
select Complex exponential
, the output is of
the form sine + j*cosine
and the port is labeled
exp. If you select Sine and
cosine
, the block shows two ports,
sin and cos.
Show phase port
— Output current phaseOutput the current phase of the accumulator when selected.
Overflow mode
— Overflow mode for fixedpoint operationsWrap
(default)Overflow mode for fixedpoint operations. Overflow mode is a readonly parameter. Fixedpoint numbers wrap around on overflow.
Rounding Mode
— Rounding mode for fixedpoint operationsFloor
(default)Rounding
mode for fixedpoint operations. Rounding
Mode is a readonly parameter with value
Floor
.
Accumulator Data Type
— Accumulator data typeBinary point
scaling
(default)Accumulator data type description. This parameter is readonly, with
value Binary point scaling
. The block defines
the fixedpoint data type using the Accumulator
Signed, Accumulator Word length, and
Accumulator Fraction length parameters.
Accumulator Signed
— Signed or unsigned accumulator data formatSigned
(default)This parameter is readonly. All output is signed format.
Accumulator Word length
— Accumulator word lengthAccumulator word length, in bits, specified as a scalar integer.
If Quantize phase is disabled, this parameter must be less than or equal to 17 bits for HDL code generation.
Accumulator Fraction length
— Accumulator fraction lengthThis parameter is readonly. The accumulator fraction length is zero bits.
The accumulator operates on integers. If the phase increment is
fixdt
type with a fractional part, the block
ignores the fractional part.
Output Data Type
— Output data typeBinary point
scaling
(default)  double
 single
Specify the output signal data type. If you select Binary
point scaling
, the block defines the fixedpoint data
type using the Output Signed, Output Word
length, and Output Fraction length
parameters.
Output Signed
— Signed or unsigned output data formatSigned
(default)This parameter is readonly. All output is signed format.
Output Word length
— Output word lengthOutput word length, in bits, specified as a scalar integer.
Output Fraction length
— Output fraction lengthOutput fraction length, in bits, specified as a scalar integer.
The NCO implementation depends on whether you select Enable look up table compression method.
Without lookup table compression, the block uses the same quartersine lookup table as the NCO block. The size of the LUT is 2^{Number of quantizer accumulator bits2}×Output word length bits.
If you do not enable Quantize phase, then Number of quantizer accumulator bits=Accumulator Word length. Consider the impact on simulator memory and hardware resources when you select these parameters.
When you select lookup table (LUT) compression, the NCO HDL Optimized block applies the Sunderland compression method. Sunderland techniques use trigonometric identities to divide each phase of the quarter sine wave into three components and express it as:
$$\mathrm{sin}(A+B+C)=\mathrm{sin}(A+B)\mathrm{cos}(C)+\mathrm{cos}(A)\mathrm{cos}(B)\mathrm{sin}(C)\mathrm{sin}(A)\mathrm{sin}(B)\mathrm{sin}(C)$$
If the quartersine phase has Q2
bits, then
the phase components A and B have a word
length of
LA=LB=ceil((Q2)/3)
.
Phase component C contains the remaining phase bits. If the phase
has 12 bits, then the quarter sine phase has 10 bits, and the components are defined
as:
A, the four most significant bits
$$(0\le A\le \frac{\pi}{2})$$
B, the next four bits
$$(0\le B\le \frac{\pi}{2}\times {2}^{4})$$
C, the remaining two least significant bits
$$(0\le C\le \frac{\pi}{2}\times {2}^{}{}^{8})$$
Given the relative sizes of A, B, and C, the equation can be approximated by:
$$\mathrm{sin}(A+B+C)\approx \mathrm{sin}(A+B)+\mathrm{cos}A\mathrm{sin}C$$
The NCO HDL Optimized block implements this equation with one LUT for and one LUT for . The second term is a fine correction factor that you can truncate to fewer bits without losing precision. Therefore, the second LUT returns a fourbit result.
With the default accumulator size of 16 bits, and the default quantized phase width of 12 bits, the LUTs use 2^{8}×16 plus 2^{6}×4 bits (4.5 kb). A quarter sine lookup table uses 2^{10}×16 bits (16 kb). This approximation is accurate within one LSB, resulting in an SNR of at least 60 dB on the output. See [1].
There are two input control signals, reset and
validIn, and one output control signal,
validOut. When reset is
true
(1
), the block sets the phase
accumulator to zero. When validIn is true
(1
), the block increments the phase. When
validIn is false
(0
),
the block stops the phase accumulator and holds its state. When
validOut is true
(1
),
the output is valid.
The latency of the NCO HDL Optimized block is six cycles.
[1] Cordesses, L., "Direct Digital Synthesis: A Tool for Periodic Wave Generation (Part 1)." IEEE Signal Processing Magazine. Volume 21, Issue 4, July 2004, pp. 50–54.
This block supports C/C++ code generation for Simulink^{®} accelerator and rapid accelerator modes and for DPI component generation.
HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

LUTRegisterResetType  The reset type of the lookup table output register. Select 
OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

When you set Dither source to
Property
, the block adds random dither
every cycle. If you generate a validation model with these settings, a
warning is displayed. Random generation of the internal dither can cause
mismatches between the models. You can increase the error margin for the
validation comparison to account for the difference. You can also
disable dither or set Dither source to
Input port
to avoid this issue.
You cannot use the NCO HDL Optimized block inside a Resettable Synchronous Subsystem.
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