This is machine translation

Translated by Microsoft
Mouseover text to see original. Click the button below to return to the English version of the page.

Note: This page has been translated by MathWorks. Click here to see
To view all translated materials including this page, select Country from the country navigator on the bottom of this page.

IFFT HDL Optimized

Computes inverse-fast-fourier-transform and generates optimized HDL code

  • Library:
  • DSP System Toolbox / Transforms

    DSP System Toolbox HDL Support / Transforms

Description

The IFFT HDL Optimized block provides two types of architectures to optimize either throughput or area.

  • Streaming Radix 2^2 — Use this architecture for high-throughput applications. This architecture supports scalar or vector input data. You can achieve giga-sample-per-second (GSPS) throughput using vector input.

  • Burst Radix 2 — Use this architecture for a minimum resource implementation, especially with large fast-fourier-transform (FFT) sizes. Your system must be able to tolerate bursty data and higher latency. This architecture supports only scalar input data.

The IFFT HDL Optimized accepts real or complex data, provides hardware-friendly control signals, and optional output frame control signals.

Ports

Input

expand all

Input data, specified as a scalar or column vector of real or complex values. Only the Streaming Radix 2^2 architecture supports a vector input. The vector size must be a power of 2, in the range from 1 to 64, and less than or equal to the FFT length.

double and single input data are allowed for simulation but not for HDL code generation.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point | single | double
Complex Number Support: Yes

This port indicates if the input data is valid. When the input valid is true (1), the block captures the value on the input data port. When the input valid is false (0), the block ignores the input data samples.

Data Types: Boolean

When reset is true (1), the block stops the current calculation and clears all internal states. The block starts a new frame when the reset is false (0) and the input valid is true (1).

Dependencies

To enable this port, select the Enable reset input port parameter.

Data Types: Boolean

Output

expand all

When input is fixed-point data type and scaling is enabled, the output data type is the same as the input data type. When the input is integer type and scaling is enabled, the output is fixed-point type with the same word length as the input integer. The output order is bit-reversed by default. If scaling is disabled, the output word length increases to avoid overflow. Only the Streaming Radix 2^2 architecture supports vector input and output. For more information, see Divide butterfly outputs by two parameter.

Data Types: fixed point | double | single
Complex Number Support: Yes

This port indicates that output data is valid. When valid is true (1), the block returns valid data on the output data port. When valid is false (0), the values on output data port are not valid.

Data Types: Boolean

This port indicates that the block is ready for a new input sample. When ready is true (1), the block accepts input data in the next time step, and when ready is false (0), the block ignores the input data in the next time step.

Dependencies

The port appears on the block when you set the Architecture parameter to Burst Radix 2.

Data Types: Boolean

When you enable this port, the block sets the start output to true (1) during the first valid cycle of a frame of output data.

Dependencies

To enable this port, select the Enable start output port parameter.

Data Types: Boolean

When you enable this port, the block sets the end output to true (1) during the last valid cycle of a frame of output data.

Dependencies

To enable this port, select the Enable end output port parameter.

Data Types: Boolean

Parameters

expand all

Main

This parameter specifies the number of data points used for one inverse-fast-fourier-transform (IFFT) calculation. For HDL code generation, the FFT length must be a power of 2 between 23 and 216.

This parameter specifies the type of architecture.

  • Streaming Radix 2^2 — Select this value to specify low-latency architecture. This architecture type supports GSPS throughput when using vector input.

  • Burst Radix 2 — Select this value to specify minimum resource architecture. This architecture type does not support vector input.

For HDL code generation, the FFT length must be a power of 2 between 23 and 216.

For more details about these architectures, see Algorithms.

This parameter specifies the complex multiplier type for HDL implementation. Each multiplication is implemented either with Use 4 multipliers and 2 adders or with Use 3 multipliers and 5 adders. The implementation speed depends on the synthesis tool and target device that you use.

This parameter returns output elements in bit-reversed order.

When you select this parameter, the output elements are bit-reversed. To return output elements in linear order, clear this parameter.

The IFFT algorithm calculates output in the reverse order to the input. If you specify the output to be in the same order as the input, the algorithm performs an extra reversal operation. For more information, see Linear and Bit-Reversed Output Order.

When you select this parameter, the block expects input data in bit-reversed order. By default, the check box is cleared and the input is expected in linear order.

The IFFT algorithm calculates output in the reverse order to the input. If you specify the output to be in the same order as the input, the algorithm performs an extra reversal operation. For more information, see Linear and Bit-Reversed Output Order.

When you select this parameter, the block implements an overall 1/N scale factor by dividing the output of each butterfly multiplication by two. This adjustment keeps the output of the IFFT in the same amplitude range as its input. If you disable scaling, the block avoids overflow by increasing the word length by 1 bit after each butterfly multiplication. The bit increase is the same for both architectures.

Data Types

This parameter allows you to select the type of rounding mode for internal fixed-point calculations. For more information about rounding modes, see rounding method. When the input is any integer or fixed-point data type, the IFFT algorithm uses fixed-point arithmetic for internal calculations. This option does not apply when the input is single or double type. Rounding applies to twiddle factor multiplication and scaling operations.

Control Ports

This parameter enables a reset input port. When you select this parameter, the input reset port appears on the block icon.

This parameter enables a port that indicates the start of output data. When you select this parameter, the output start port appears on the block icon.

This parameter enables a port that indicates the end of output data. When you select this parameter, the output end port appears on the block icon.

Block Characteristics

Data Types

double | fixed point | integer | single

Direct Feedthrough

no

Multidimensional Signals

no

Variable-Size Signals

no

Zero-Crossing Detection

no

Algorithms

expand all

Extended Capabilities

See Also

Blocks

System Objects

Introduced in R2014a