(Removed) Radix2 FFT with decimationinfrequency (DIF) — optimized for HDL code generation
The HDL Streaming FFT block has been removed. Use the FFT HDL Optimized block with the Architecture parameter
set to Streaming Radix 2^2
, instead. For more information, see
Implement FFT for FPGA Using FFT HDL Optimized Block.
Obsolete
dspobs
The HDL Streaming FFT block returns results identical to results returned by the Radix2 DIF algorithm of the FFT block.
The block has these input ports:
din
: The input data signal. The coder requires a complex
fixedpoint signal.
start
: Boolean control signal. When start
asserts true (1), the HDL Streaming FFT block initiates processing of a data
frame.
The block has these output ports:
dout
: Data output signal.
dvalid
: Boolean control signal. The HDL Streaming FFT block
asserts this signal true (1) when a stream of valid output data is available at
the dout
port.
ready
: Boolean control signal. The HDL Streaming FFT block
asserts this signal true (1) to indicate that it is ready to process a new
frame.
The HDL Streaming FFT block operates in one of two modes:
Continuous data streaming mode: In this mode, the HDL
Streaming FFT block expects to receive a continuous stream of data at
din
. After an initial delay, the block produces a continuous
stream of data at dout
.
Noncontinuous data streaming mode: In this mode, the
HDL Streaming FFT block receives noncontinuous bursts of streaming data at
din
. After an initial delay, the block produces
noncontinuous bursts of streaming data at dout
.
The behavior of the control signals determines the timing mode of the block.
Assertion of the start
signal (active high) triggers processing
by the HDL Streaming FFT block. To initiate continuous data stream processing, assert
the start
signal in one of the following ways:
Hold the start signal high (as shown in figure “Continuous Data Streaming With Start Signal Held High”).
Pulse the start signal every N clock cycles, where N is the FFT length (as shown in figure “Continuous Data Streaming With Pulsed Start Signal”).
One clock cycle after the start
trigger, the block begins to
load data at din
. After the first frame of streaming data, the
block starts to receive the next frame of streaming data.
Meanwhile, the block performs the FFT calculation on the incoming data frames and
outputs the results continuously at dout
. The HDL Streaming FFT
block asserts and deasserts the ready
and
dvalid
signals automatically. The block asserts
dvalid
high whenever the output data stream is valid. The block
asserts ready
high to indicate that the block is ready to load a
new data frame. When ready
is low, the block ignores the
start
signal.
The following figures illustrate continuous data streaming. Each data frame corresponds to a stream of N input data values, where N is the FFT length.
Continuous Data Streaming With Start Signal Held High
Note
The start
signal can be a single cycle pulse; it need not be
held high for the entire data frame. When processing for a frame begins, further
pulses on start
do not affect
processing of that frame. However, a start
pulse must occur at
the beginning of each data frame.
Continuous Data Streaming With Pulsed Start Signal
In this mode, the HDL Streaming FFT block receives continuous bursts of streaming
data at din
. After an initial delay, the block produces
noncontinuous bursts of streaming data at dout
. Breaks occur
between data frames when the following condition exist:
The start
signal does not assert every N clock cycles
(where N is the FFT length)
The start
signal is not continuously held high.
Noncontinuous data streaming mode allows you more flexibility in determining the intervals between input data streams.
The initial delay of the HDL Streaming FFT block is the interval between the following times:
The time the block begins to receive the first frame of input data
The time the block asserts dvalid
and produces the first
valid output data.
The initial delay represents the time the block uses to load a data frame, calculate the FFT, and output the beginning of the first output frame. The following figure illustrates the initial delay.
If you select the block option Display computed initial delay on mask, the block icon displays the initial delay. The display represents the delay time as Z^{n}, where n is the delay time in samples.
FFT Length
Default: 1024
The FFT length must be a power of 2, in the range 2^{3} to 2^{16}.
Rounding mode
Default: Floor
The HDL Streaming FFT block supports all rounding modes of the FFT block. See also the FFT block reference.
Overflow mode
Default: Wrap
The HDL Streaming FFT block supports all overflow modes of the FFT block. See also the FFT block reference.
Sine table
Default: Same word length as input
Choose how you specify the word length of the values of the sine table. The fraction length of the sine table values is equal to the word length minus one.
When you select Same word length as input
, the word
lengths of the sine table values match the word lengths of the block
inputs.
When you select Specify word length
, you can enter
the word length of the sine table values, in bits, in the Sine table
word length field. The sine table values do not obey the
Rounding mode and Overflow mode
parameters. They always saturate and round to
Nearest
.
Product output
Default: Same as input
Use this parameter to specify how you want to designate the product output word and fraction lengths:
When you select Same as input
, these characteristics
match the characteristics of the input to the block.
Binary point scaling
: Enter the word length and the
fraction length of the product output, in bits, in the Product word
length and Product fraction length
fields.
Accumulator
Default: Same as input
Use this parameter to specify how you want to designate the accumulator word and fraction lengths:
When you select Same as product output
, these
characteristics match the characteristics of the product output.
When you select Same as input
, these characteristics
match the characteristics of the input to the block.
Binary point scaling
: Enter the word length and the
fraction length of the accumulator, in bits, in the Accumulator word
length and Accumulator fraction length
fields.
Output
Default: Same as input
Choose how you specify the output word length and fraction length:
Same as input
: these characteristics match the
characteristics of the input to the block.
Binary point scaling
: lets you enter the word length
and fraction length of the output, in bits, in the Output word
length and Output fraction length
fields.
Output in bitreversed order
Default: Off
On: The output data stream is in bitreversed order.
Off: The output data stream is in natural order.
For more information about the effects of bit reversal, see Linear and BitReversed Output Order.
Display computed initial delay on mask
Default: Off
On: The block icon displays the initial delay as Z^{n}, where n is the delay time in samples.
Off: The block icon does not display the initial delay.
Note
Sine table, Product output, Accumulator, and Output do not support:
Inherit via internal rule
Slope and bias scaling
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
