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dsp.HDLFIRFilter System object

Finite impulse response filter—optimized for HDL code generation

Description

The dsp.HDLFIRFilter System object™ models FIR filter architectures optimized for HDL code generation. The object accepts one input sample at a time. It provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the object models architectural latency including pipeline registers and resource sharing. The latency between valid input data and the corresponding valid output data depends on the number and values of the filter coefficients, and on the resource-sharing factor.

The object provides two hardware architectures. The direct form systolic architecture provides a configurable serial implementation or a fully parallel implementation. This architecture makes efficient use of Intel® and Xilinx® DSP blocks. The direct form transposed architecture is a fully parallel implementation and is suitable for FPGA and ASIC applications. Both fully parallel architectures automatically optimize hardware resources by sharing multipliers when coefficients have the same absolute values, such as in symmetric or anti-symmetric filters. The fully parallel architectures also remove the multipliers for zero-valued coefficients such as in half-band filters and Hilbert transforms. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.

For a FIR filter with programmable or complex coefficients or with multichannel or frame-based inputs, use the dsp.FIRFilter System object instead of this System object.

To filter input data with an HDL-optimized FIR filter:

  1. Create the dsp.HDLFIRFilter object and set its properties.

  2. Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects? (MATLAB).

Creation

Syntax

firFilt = dsp.HDLFIRFilter
firFilt = dsp.HDLFIRFilter(num)
firFilt = dsp.HDLFIRFilter(___,Name,Value)

Description

firFilt = dsp.HDLFIRFilter creates an HDL-optimized discrete FIR filter System object, firFilt, with default filter properties.

firFilt = dsp.HDLFIRFilter(num) creates the filter with the Numerator property set to num.

firFilt = dsp.HDLFIRFilter(___,Name,Value) creates the filter with properties set using one or more name-value pairs. Enclose each property name in single quotes.

For example:

Numerator = firpm(10,[0,0.1,0.5,1],[1,1,0,0]);
fir = dsp.HDLFIRFilter(Numerator,'FilterStructure','Direct form transposed');
...
[dataOut,validOut] = fir(dataIn,validIn);

Properties

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Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects (MATLAB).

Main

Discrete FIR filter coefficients, specified as a vector of numeric real values. You can also specify the vector as a workspace variable, or as a call to a filter design function. Complex coefficients are not supported. When the input data type is a floating-point type, the object casts the coefficients to the same data type as the input. When the input data type is an integer type or a fixed-point type, you can modify coefficient type casting details using the CoefficientsDataType property.

Example: 'Numerator',firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0]) defines the coefficients using a linear-phase filter design function.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

HDL filter architecture, specified as one of these structures:

  • 'Direct form systolic' – This architecture provides parallel or serial filter implementation. It makes efficient use of Intel and Xilinx DSP blocks. The filter implementation and resource optimization depend on the setting of the Sharing property.

    • false – The object implements a fully parallel filter. The implementation shares multipliers for symmetric and antisymmetric coefficients and removes multipliers for zero-valued coefficients. For architecture and performance details, see Fully Parallel Systolic Architecture.

    • true – The object implements a serial filter and provides options for tradeoffs between throughput and resource utilization. Set the SharingFactor property to N to reduce the overall DSP resource utilization by a factor of N. In this case, the object can process only input samples that are at least N cycles apart. For this implementation, the object provides an output argument, ready, that indicates when the object is ready for new input data. For architecture and performance details, see Partly Serial Systolic Architecture (1 < N < L) and Fully Serial Systolic Architecture (N ≥ L).

  • 'Direct form transposed' – This architecture is a fully parallel implementation that minimizes multipliers by sharing multipliers for any two or more coefficients that have equal absolute values. It also removes multipliers for zero-valued coefficients and is suitable for FPGA and ASIC applications. This architecture does not support use of the Sharing property. For architecture and performance details, see Fully Parallel Transposed Architecture.

Enable resource sharing, specified as false or true. To reduce the overall DSP resource utilization on the FPGA, set this property to true. Then set the SharingFactor property to the value by which you want to reduce the number of DSPs.

When you set this property to true, the object returns the ready argument, and you cannot use either the ResetInputPort or the HDLGlobalReset properties.

Dependencies

To enable this property, set the FilterStructure property to 'Direct form systolic'.

Reduction factor for number of DSPs, specified as a positive integer. A sharing factor of N indicates that the object reduces DSP resource utilization by a factor of N. In this case, the object can process an input sample only every N calls to the object.

Dependencies

To enable this property, set the FilterStructure property to 'Direct form systolic' and set the Sharing property to true.

Data Types

Rounding method for type-casting the output, specified as 'Floor', 'Ceiling', 'Convergent', 'Nearest', 'Round', or 'Zero'. The rounding method is used when casting the output to the data type specified by the OutputDataType property. When the input data type is floating point, the object ignores the RoundingMethod property. See Rounding Modes for more details.

Overflow handling for type-casting the output, specified as 'Wrap' or 'Saturate'. Overflow handling is used when casting the output to the data type specified by the OutputDataType property. When the input data type is floating point, the object ignores the OverflowAction property. See Overflow Handling for more details.

Data type of discrete FIR filter coefficients, specified as 'Same word length as input', or as a numerictype object. To specify the object, call numerictype(s,w,f), where

  • s is 1 for signed and 0 for unsigned.

  • w is the word length in bits.

  • f is the number of fractional bits.

The object type-casts the filter coefficients of the discrete FIR filter to the specified data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is floating point, the object ignores the Coefficients property.

Data type of discrete FIR filter output, specified as 'Same word length as input', 'Full precision', or as a numerictype object. To specify the object, call numerictype(s,w,f), where

  • s is 1 for signed and 0 for unsigned.

  • w is the word length in bits.

  • f is the number of fractional bits.

The object type-casts the output of the discrete FIR filter to the specified data type. The quantization uses the settings of the RoundingMethod and OverflowAction properties. When the input data type is floating point, the object ignores the OutputDataType property.

The object increases the word length for full precision inside each filter tap and casts the final output to the specified type. The maximum final internal data type (WF) depends on the input data type (WI), the coefficient data type (WC), and the number of coefficients (L) and is given by

WF = WI + WC + ceil(log2(L))

Usually, the actual full-precision internal word length is smaller than WF because the values of the coefficients limit the potential growth.

Control Arguments

When you set this property to true, use the reset argument when you call the object. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see Tips.

Dependencies

To enable this property, set the Sharing property to false.

Set this property to true to connect the generated HDL global reset signal to the data path registers. This property does not change the arguments of the object or modify simulation behavior in MATLAB®. When this property is set to false, the generated HDL global reset clears only control path registers. The generated HDL global reset can be synchronous or asynchronous depending on your HDL code generation settings.

For more reset considerations, see Tips.

Dependencies

To enable this property, set the Sharing property to false.

Usage

Syntax

[dataOut,validOut] = firFilt(dataIn,validIn)
[dataOut,validOut,ready] = firFilt(dataIn,validIn)
[dataOut,validOut] = firFilt(dataIn,validIn,reset)

Description

[dataOut,validOut] = firFilt(dataIn,validIn) filters the input data only when validIn is true.

example

[dataOut,validOut,ready] = firFilt(dataIn,validIn) returns ready set to true when the object is ready to accept new input data on the next call.

The object returns the ready argument only when you set the Sharing property to true. For example:

firFilt = dsp.HDLFIRFilter(Numerator,'Sharing',true, ...
            'SharingFactor',10)
...
for k=1:length(dataIn)
    [dataOut,validOut,ready] = firFilt(dataIn(k),validIn(k));

[dataOut,validOut] = firFilt(dataIn,validIn,reset) filters data when reset is false. When reset is true, the object resets the filter registers. The object expects the reset argument only when you set the ResetInputPort property to true. For example:

firFilt = dsp.HDLFIRFilter(Numerator,'ResetInputPort',true)
...
% reset the filter
firFilt(0,false,true);
for k=1:length(dataIn)
    [dataOut,validOut] = firFilt(dataIn(k),validIn(k),false);

Input Arguments

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Input data, specified as a real or complex scalar. When the input data type is integer or fixed point, the object uses fixed-point arithmetic for internal calculations. double and single are accepted for simulation but not for HDL code generation.

Data Types: fi | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

Validity of the input data, specified as a logical scalar. The first argument, dataIn, is treated as valid only when validIn is 1 (true).

Data Types: logical

Output Arguments

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Filtered output data, returned as a real or complex scalar. When the input data is floating point, the output data inherits the data type of the input data. When the input data is integer or fixed point, the OutputDataType property determines the output data type.

Data Types: fi | single | double
Complex Number Support: Yes

Validity of the output data, returned as a logical scalar. The object sets validOut to 1 (true) with each valid output data on dataOut.

Data Types: logical

Indicator of whether the object is ready for new input data, returned as a logical scalar. The object sets ready to true to indicate that it is ready to accept new input data on the next call. The object returns this value only when the Sharing property is set to true.

Data Types: logical

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

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getLatencyLatency of FIR filter
stepRun System object algorithm
releaseRelease resources and allow changes to System object property values and input characteristics
resetReset internal states of System object

Examples

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Create an HDL FIR filter System object with default settings.

firFilt = dsp.HDLFIRFilter;

Create an input signal of some random noise, and allocate memory for outputs.

L = 100;
dataIn = randn(L,1);
dataOut = zeros(L,1);
validOut = false(L,1);

Call the object on the input signal, asserting that the input data is always valid. The object processes one data sample at a time.

for k=1:L
    [dataOut(k),validOut(k)] = firFilt(dataIn(k),true);
end

Operate a 31-tap lowpass filter with resource sharing.

Design the filter coefficients. Then create an HDL FIR filter System object. Enable resource sharing and the ready output port.

numerator = firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0]);
sharingFactor = 10;
firFilt = dsp.HDLFIRFilter('Numerator',numerator, ...
    'Sharing',true,'SharingFactor',sharingFactor);

The specified sharingFactor indicates that the filter requires 10 time steps to calculate each output. Create input signals dataIn and validIn such that new data is applied only every sharingFactor time steps.

L = 16;
x = fi(randn(L,1),1,16);
dataIn = zeros(L*sharingFactor,1,'like',x);
dataIn(1:sharingFactor:end) = x;
validIn = false(L*sharingFactor,1);
validIn(1:sharingFactor:end) = true;

Create a LogicAnalyzer object to view the inputs and outputs

la = dsp.LogicAnalyzer('NumInputPorts',5, ...
    'SampleTime',1,'TimeSpan',length(dataIn));
tags = getDisplayChannelTags(la);
modifyDisplayChannel(la,tags{1},'Name','dataIn');
modifyDisplayChannel(la,tags{2},'Name','validIn');
modifyDisplayChannel(la,tags{3},'Name','dataOut');
modifyDisplayChannel(la,tags{4},'Name','validOut');
modifyDisplayChannel(la,tags{5},'Name','ready');

Call the filter System object on the input signals, and view the results in the Logic Analyzer.

for k=1:length(dataIn)
    [dataOut,validOut,ready] = firFilt(dataIn(k),validIn(k));
    la(dataIn(k),validIn(k),dataOut,validOut,ready)
end

The object models HDL pipeline registers and resource sharing. Therefore, there is an initial delay before the object returns valid output samples.

To generate HDL code from a System object™, create a function that contains and calls the object.

Create Function

Write a function that creates and calls an 11-tap HDL FIR filter System object. You can generate HDL from this function.

function [dataOut,validOut] = HDLFIR11Tap(dataIn, validIn)
%HDLFIR11Tap
% Process one sample of data using the dsp.HDLFIRFilter System
% object. 
% dataIn is a fixed-point scalar value. 
% You can generate HDL code from this function.
    persistent fir
    if isempty(fir)
        Numerator = firpm(10,[0 0.1 0.5 1],[1 1 0 0]);
        fir = dsp.HDLFIRFilter(Numerator);
    end
    [dataOut,validOut] = fir(dataIn,validIn);    
end


Create Test Bench for Function

Clear the workspace, create an input signal of some random noise, and allocate memory for outputs.

clear variables
clear HDLFIR11Tap
L = 200;
dataIn = fi(randn(L,1),1,16);
validIn = ones(L,'logical');
dataOut = zeros(L,1);
validOut = false(L,1);

Call the function on the input signal.

for k = 1:L
    [dataOut(k),validOut(k)] = HDLFIR11Tap(dataIn(k), validIn(k));
end

Plot the signals with the Logic Analyzer.

la = dsp.LogicAnalyzer('NumInputPorts',3,'SampleTime',1,'TimeSpan',L);
tags = getDisplayChannelTags(la);
modifyDisplayChannel(la,tags{1},'Name','dataIn','Format','Analog','Height',50);
modifyDisplayChannel(la,tags{2},'Name','dataOut','Format','Analog','Height',50);
modifyDisplayChannel(la,tags{3},'Name','validOut');
la(dataIn,dataOut,validOut)

The latency of the object varies with the architecture and the coefficient values. Use the getLatency function to find the latency of a particular configuration. The latency is the number of cycles between the first valid input and the first valid output, assuming that the input is contiguous valid samples.

Create a new dsp.HDLFIRFilter object and request the latency. The default architecture is fully parallel systolic. The default data type for the coefficients is 'Same as input data type'. Therefore, when you call getLatency, you must specify an input data type. The object casts the coefficient values to the input data type, then checks for zero and same-absolute-value coefficients.

Numerator = firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0]);
Input_type = numerictype(1,16);
hdlfir = dsp.HDLFIRFilter(Numerator);
L_sysp = getLatency(hdlfir,Input_type)
L_sysp = 23

Check the latency for a partly serial systolic implementation.

hdlfir = dsp.HDLFIRFilter(Numerator,'Sharing',true,'SharingFactor',10);
L_syssf10 = getLatency(hdlfir,Input_type)
L_syssf10 = 17

When you select a fully parallel transposed architecture, the latency is always 6 cycles.

hdlfir = dsp.HDLFIRFilter(Numerator,'FilterStructure','Direct form transposed');
L_trans = getLatency(hdlfir,Input_type)
L_trans = 6

Tips

Reset Behavior

  • By default, with no reset property set to true, the dsp.HDLFIRFilter object connects the generated HDL global reset to only control path registers. The two reset properties for fully parallel filter implementations, ResetInputPort and HDLGlobalReset, connect a reset signal to the data path registers. Resetting data path registers can reduce synthesis performance because of the additional routing and loading on the reset signal.

  • The ResetInputPort property provides a reset argument when you call the object. The reset signal implements a local synchronous reset of the data path registers.

  • The HDLGlobalReset property connects the generated HDL global reset signal to the data path registers. This property does not change the arguments of the object or modify simulation behavior in MATLAB. The generated HDL global reset can be synchronous or asynchronous depending on your HDL code generation settings. Selecting an asynchronous global reset moves registers out of the DSP blocks and increases resource use.

  • When you set both the ResetInputPort and HDLGlobalReset properties to true, both the global and local reset signals clear the control and data path registers.

  • To enable the ResetInputPort and HDLGlobalReset properties, you must set the Sharing property to false.

Algorithms

This object implements the algorithms described on the Discrete FIR Filter HDL Optimized block reference page.

Introduced in R2017a