Recommendation 1: Use a Single-Rate Model
Most applications that you target the HDL code for might not require such a large rate differential. In that case, it is recommended that you use a single-rate model. In this example, you can change the sample rate of the Constant block inside the hdlcoder_multirate_high_differential Subsystem to be the same as that of the base model.
Open this model that has the sample time of the Constant block changed to 10E-06, which is the same sample time as the base sample time of the model.
When you compile the model and double-click the hdlcoder_singlerate Subsystem, you see that the signal paths in the model operate at the same sample time of 10E-06.
Generate HDL code for the hdlcoder_singlerate Subsystem and check the output log.
You see that the output latency has decreased significantly. Now open the generated model. At the MATLAB™ command line, enter gm_hdlcoder_singlerate. When you compile the model and double-click the hdlcoder_singlerate Subsystem, the model looks as displayed by the sample time legend.
The generated HDL code is now optimal and uses few registers. Therefore, you can deploy the design to target FPGA platforms.