Recommendation 2: Reduce the Rate Differential
If you want to use a multirate model, it is recommended that you reduce the rate differential. Rate differential corresponds to the ratio of the fastest to the slowest clock rate in your design. If your target application requires two signal paths such that one signal path runs in time units of nanoseconds (ns) and the other signal path runs in time units of microseconds (us), you can choose to retain the multirate paths in your model. Be aware that delay balancing can introduce a significantly large number of registers to balance the signal paths.
In this example, you can change the sample rate of the Constant block inside the hdlcoder_multirate_high_differential Subsystem to reduce the rate differential.
Open this model that has the sample time of the Constant block changed to 0.01.
When you compile the model and double-click the hdlcoder__multirate_medium_differential Subsystem, you see that the rate differential between the two signal paths is equal to 1000.
Generate HDL code for the hdlcoder_multirate_medium_differential Subsystem and check the output log.
Open the generated model. At the MATLAB™ command line, enter gm_hdlcoder_multirate_medium_differential. When you compile the generated model and double-click the hdlcoder_multirate_medium_differential Subsystem, the model is as displayed by the sample time legend.
The model has a large number of registers, approximately 1000, in the fast clock rate path. The additional cost of registers is expected when you have a control logic that runs at a sample rate that is 1000 times faster than the sample rate of the system. When you deploy the generated code to a target platform, be aware of the constraints in hardware resources on the target platform. This recommendation offers a trade-off between generating optimal HDL code and targeting practical FPGA applications that might require an extremely large rate differential.