Generate HDL Code from Simscape Models
This example uses a halfwave rectifier model to illustrate how you can develop your plant model in Simscape™ and use Simscape HDL Workflow Advisor to generate HDL code for your model.
- Why Generate HDL Code?
- Simscape Example models for HDL Code generation
- Guidelines for Modeling Simscape for HDL Compatibility
- The Halfwave Rectifier Model
- Simulate and Verify Functionality of Simscape Algorithm
- Open Simscape HDL Workflow Advisor
- Run Simscape HDL Workflow Advisor
- Open HDL Implementation Model
- Generate HDL Code and Validation Model
Why Generate HDL Code?
To perform hardware-in-the-loop (HIL) simulation with smaller timesteps and increased accuracy, you can deploy the plant models to the FPGAs on board the Speedgoat I/O modules. By using the Simscape HDL Workflow Advisor, you can generate an HDL implementation model. You can then generate HDL code for the implementation model and deploy the generated code onto the FPGA platforms. Using this capability, you can model and deploy complex physical systems in Simscape that previously took long time to model by using Simulink™ blocks.
Simscape Example models for HDL Code generation
For HDL code generation, you can design your own Simscape algorithm or choose from a list of example models that are created in Simscape. The example models include:
- Boost Converter
- Bridge Rectifier
- Buck Converter
- Halfwave Rectifier
- Three Phase Rectifier
- Two Level Converter Ideal
- Two Level Converter Igbt
All examples files are prefixed with sschdlex and have Example as a suffix. For example, to open the Boost Converter model, enter:
Guidelines for Modeling Simscape for HDL Compatibility
1. Create a Simscape model by using switched linear blocks. Add Simulink-PS Converter blocks at the input ports and PS-Simulink Converter blocks at the output ports.
2. Configure the solver options for HDL code generation by using a Solver Configuration block. In the block parameters of this block:
- Select Use local solver.
- Use Backward Euler as the Solver type.
- Specify a discrete sample time, Ts.
3. Enclose the blocks inside a Subsystem and provide the test inputs.
4. Configure the model for HDL code generation by running the hdlsetup function. hdlsetup configures the solver settings, such as using a fixed-step solver, specifies the simulation start and stop times, and so on. To run the command for your current_model:
5. Verify Simscape model compatibility by using the simscape.findNonLinearBlocks function. This function detects the nonlinear blocks in your Simscape model. Provide the path to your Simscape model as an argument to this function. It returns the names of nonlinear blocks.
To verify presence of nonlinear blocks in Half Wave Rectifier Model, enter:
The number of linear or switched linear networks in the model is 1. ans = 0×0 empty cell array
The Simscape HDL Workflow Advisor does not work for Simscape models that contain:
- Mode charts
- Run-time parameters
- Periodic sources
- Nonlinearities that result from network connectivity. If the model contains a nonlinearity of this sort, the sschdladvisor function might run all tasks to completion, but generate a zero-value output.
The Halfwave Rectifier Model
To open the half-wave rectifier model, enter:
load_system('sschdlexHalfWaveRectifierExample') open_system('sschdlexHalfWaveRectifierExample/Simscape_system') set_param('sschdlexHalfWaveRectifierExample', 'SimulationCommand', 'update');
The Simscape model uses switched linear blocks such as Diode and Resistor to model the design. The model has Simulink-PS Converter blocks at the input port and PS-Simulink converter blocks at the output ports. To verify that the solver settings are configured correctly, open the Solver Configuration block.
At the top level of the model, you see a Simscape_system block that models the half-wave rectifier algorithm. The model accepts a Sine Wave input, uses a Rate Transition block to discretize the continuous time input, and has a Scope block that calculates the output. To see the input stimulus and the output from the model, connect the Sine Wave input to the Scope block.
To configure the half-wave rectifier model for HDL compatibility, enter:
Simulate and Verify Functionality of Simscape Algorithm
To see the simulation results, simulate the model and then open the Scope block.
This figure shows simulation results with the sine wave input and the outputs from Simscape_system.
Open Simscape HDL Workflow Advisor
To generate an HDL implementation model from which you can generate code, use the Simscape HDL Workflow Advisor. To open the Advisor, run this command:
This updates the model advisor cache and opens the Simscape HDL Workflow Advisor.
The Advisor contains these folders:
- Code Generation compatibility: The tasks in this folder check whether:
- You have set the Solver Configuration settings correctly.
- You used switched Linear blocks in your model.
To verify that the model is compatible for HDL code generation, run the tasks in this folder. If your model contains Nonlinear blocks, the advisor reports a failure and provides links to the nonlinear blocks in your model. To continue the workflow, replace the nonlinear blocks with switched linear blocks.
- State-space conversion: To convert your Simscape model to an abstract discrete state-space representation, run the tasks in this folder. This task represents the model in the form of linear modes. Each mode is represented by a set of state-space matrices. If this task passes, it displays the number of parameters, modes, and so on. The number of modes is limited by the number of switches present in your Simscape model. The maximum number of modes possible are 2^ (number of switches). All the modes that the Advisor generates are executed as per the input parameters by using a switching logic. A valid number of modes are selected depending on the design of your Simscape model.
- Implementation model generation: To generate an implementation model from the discrete state-space representation, run this task. If the task passes, it provides a link to the implementation model.
Run Simscape HDL Workflow Advisor
In the Simscape HDL Workflow Advisor, right-click the Generate implementation model task and select Run to Selected Task.
The switched linear workflow arrives at a state-space representation for every mode in a physical system. The solver method refers to the algorithm to determine the correct mode for the next time step. It is currently set to iterative, which means that the solver performs multiple computations to arrive at the correct mode. The number of iterations refer to the number of times the Simscape model is executed per mode. The Simscape HDL Workflow Advisor generates the number of iterations, required for the Simscape model under consideration, automatically.
If the task passes, you see a link to the implementation model.
In some cases, your Simscape algorithm might not be compatible for generating an implementation model by using the Simscape HDL Workflow Advisor. In such cases, running certain tasks in the Advisor can result in the task to fail. To learn how to make the model HDL-Compatible, see
Open HDL Implementation Model
To see the implementation model, in the Generate implementation model task, click the link.
The model contains two subsystems. The Subsystem block contains the Simscape algorithm that you modeled. From and Goto blocks inside this Subsystem provide the same Sine Wave input to the HDL Subsystem.
The HDL Subsystem models the state-space representation that you generated from the Simscape model. The ports of this Subsystem use the same name as the Simulink-PS Converter and PS-Simulink Converter blocks in your original Simscape model. If you navigate inside this Subsystem, you see several delays, adders, and Matrix Multiply blocks that model the state-space equations.
open_system('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx/HDL Subsystem/HDL Algorithm')
To simulate the HDL Implementation model, enter this command:
Open the scope block to view results.
The simulation results from the HDL implementation model matches that of the original plant model. Therefore, we can verify that the plant simulation model is correctly transformed into an HDL implementation model.
HDL code is generated for the HDL Subsystem block inside this model.
Generate HDL Code and Validation Model
The HDL model and subsystem parameter settings are saved by using this command:
%% Set Model 'gmStateSpaceHDL_sschdlexHalfWaveRectifierEx' HDL parameters hdlset_param('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx', 'FloatingPointTargetConfiguration', hdlcoder.createFloatingPointTargetConfig('NativeFloatingPoint')); hdlset_param('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx', 'MaskParameterAsGeneric', 'on'); hdlset_param('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx', 'Oversampling', 100); % Set SubSystem HDL parameters hdlset_param('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx/HDL Subsystem', 'FlattenHierarchy', 'on');
The model uses single data types and generates HDL code in native floating-point mode. Floating-point operators can introduce delays. Because the design contains feedback loops, for the model transformation advisor to allocate enough delays for the operators inside the feedback loops, the model uses clock-rate pipelining in conjunction with a large value for the Oversampling factor. An Oversampling factor of 100 and the clock-rate pipelining optimization is saved for this model.
For more information, see:
Before you generate HDL code, it is recommended to enable generation of the validation model. The validation model compares the output of the generated model after code generation to the original model. To learn more, see Generated Model and Validation Model.
Run these commands to save validation model generation settings on your Simulink model:
HDLmodelname = 'gmStateSpaceHDL_sschdlexHalfWaveRectifierEx'; hdlset_param(HDLmodelname, 'TargetDirectory', 'C:/Temp/hdlsrc'); hdlset_param(HDLmodelname, 'GenerateValidationModel', 'on');
To generate HDL code, run this command:
The generated HDL code and validation model is saved in C:/Temp/hdlsrc directory. The generated code is saved as HDL_Subsystem_tc.vhd. To open the validation model, click the link to gm_gmStateSpaceHDL_sschdlexHalfWaveRectifierEx_vnl.slx.
Open the Compare block at the output of HDL Subsystem_vnl Subsystem of the validation model. Then, open the Assert_Out1 block. To see the simulation results after HDL code generation, open the Compare: Out1 Scope block:
The top graph represents the output of our generated model. The middle graph represents the output of the implementation model. Because the output generated by both models is identical, the error between them is zero, which is represented in the last graph.
Optionally, you can deploy the HDL code on a hardware platform. For more information, see Deploy Simscape plant models to Speedgoat FPGA IO modules.