HDL support is provided for Gamma correction in Vision HDL Toolbox™. This example demonstrates the functionality of the pixel-stream Gamma Corrector block and compares the results with
Utilize RAM resources in your FPGA design using HDL Coder™.
Build an LTE compliant OFDM Modulator and Detector for implementation with HDL Coder™, and use LTE Toolbox™ to verify the HDL implementation model.
Instantiate multiple top-level synchronous clock input ports in HDL Coder.
Use Xilinx® System Generator for DSP with HDL Coder™.
Use HDL Coder™ to check, generate and verify HDL for a fixed-point CORDIC model implementing sin and cos trigonometric functions using the MATLAB Function Block.
Effectively use the MATLAB Function block to model commonly used hardware algorithms using HDL Coder™. An HDL design patterns library is used to show the features of MATLAB Coder supported
Use the Altera® DSP Builder Advanced Blockset with HDL Coder™.
Optimize the QPSK transmitter modeled in the QPSK Transmitter and Receiver example for HDL code generation and hardware implementation.
Demonstrates how to generate HDL code for a programmable FIR filter. You can program the filter to a desired response by loading the coefficients into internal registers using the host
HDL code generation support for the Viterbi Decoder block. It shows how to check, generate, and verify the HDL code you generate from a fixed-point Viterbi Decoder model. This example also
Optimize the QPSK receiver modeled in QPSK Transmitter and Receiver example for HDL code generation and hardware implementation. The HDL-optimized model shows a QPSK receiver that
A hardware friendly model that receives beacon frames in an 802.11 wireless local area network (WLAN) as described in [ 1 ]. For more information refer to the IEEE 802.11 WLAN - Beacon Frame
Implement a 64-QAM transmitter and receiver for HDL code generation and hardware implementation. These models are based on the models HDL Optimized QPSK Transmitter and HDL Optimized QPSK
Demonstrates how to generate HDL code for a discrete FIR filter with multiple input data streams.
Use the Vision HDL Toolbox Histogram library block to implement histogram equalization.
When designing video processing algorithms, an important concern is the quality of the incoming video stream. Real-life video systems, like surveillance cameras or camcorders, produce
Demonstrates how to detect and highlight object edges in a video stream. The functionality of the pixel-stream Sobel Edge Detector and Video Alignment blocks is verified by comparing the
Implement a front-end module of an image processing design. This front-end module removes noise and sharpens the image to provide a better initial condition for the subsequent processing.
Use the State Control block to generate hardware-friendly HDL code using HDL Coder.
There are numerous applications where the input video is divided into several zones, and the statistic is then computed over each zone. For example, many auto-exposure algorithms compute
In this example you will review a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Machine (PMSM) implemented using single-precision floating-point
Use distributed pipelining to optimize a design for speed in HDL Coder.
Balance delays in specific parts of a design, without balancing delays on the entire design.
How HDL Coder can automatically balance delays within a model. HDL Coder may introduce additional delays in the HDL implementation for a given model. These delays may be introduced by either
Apply clock rate pipelining to optimize slow paths in your design and thereby reduce latency, increase clock frequency and decrease area usage. For more information on how to use clock-rate
Combine operations replace several operations with one equivalent operation. Examples of this optimization technique include replacement of a Sin block and a Cos block by a Sincos block.
Constant folding removes redundant operations in your design by evaluating constant subexpressions in advance. This optimization technique identifies Simulink® blocks in your model
Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see the
How HDL Coder™ manages the execution of operations in the context of clock rate pipelining. By default, if resource sharing is applied in a region of the design operating at the fastest base
Dead code elimination removes a part of the HDL code that is not accessed or is unreachable because of modeling constructs.
Generate a cosimulation model in of HDL Coder and integrate the generated HDL code into an HDL Verifier™ workflow. Automation of cosimulation model generation enables seamless