Implementing a Wireless Receiver on an FPGA, Part 3: Implementing and Verifying the Design on Target Hardware

해당 시리즈: Implementing a Wireless Receiver on an FPGA

Frank Liu, MathWorks
Idin Motedayen-Aval, MathWorks
Jason Bryan, MathWorks

In the final section of this three-part series, we implement and verify the design on target hardware by doing the following:

  • Develop an implementation friendly architecture from the behavioral model
  • Convert the floating point model into fixed-point
  • Automatically generate HDL code and integrate the code with target hardware
  • Verify the design using HDL co-simulation and FPGA-in-the-loop on a Xilinx Spartan-6 Evaluation Kit

Product Focus

  • HDL Coder
  • Fixed-Point Designer
  • HDL Verifier

녹화된: 2012년8월29일

시리즈: Implementing a Wireless Receiver on an FPGA

Part 1: Creating and Verifying a Baseline Wireless Transmitter and Receiver Using Simulink
In Part 1 of our series, we begin by building a baseline QPSK Model using Simulink.

Part 2: Elaborating and Prototyping the Transmitter and Receiver Model
In Part 2 of this three-part series, we elaborate and prototype the QPSK model built in part 1.

Part 3: Implementing and Verifying the Design on Target Hardware
In the final section of this three-part series, we implement and verify the design on target hardware.