Filter Design HDL Coder
The generated VHDL and Verilog code adheres to a clean HDL coding style that enables architects and designers to quickly customize the code if needed. The test bench feature increases confidence in the correctness of the generated code and saves time spent on test bench implementation.
Filter Design HDL Coder is integrated with DSP System Toolbox to provide a unified design and implementation environment. You can design filters and generate VHDL and Verilog code either from the MATLAB command line or from DSP System Toolbox using the Filter Design and Analysis app or the Filter Builder app.
The design entry input to Filter Design HDL Coder is a quantized filter that you create in one of two ways:
Filter Design HDL Coder supports several important filter structures, including:
Discrete-time finite impulse response (FIR), which includes symmetric, anti-symmetric, and transposed structures
Second-order section (SOS) infinite impulse response (IIR), which includes direct form I, II, and transposed structures
Multirate filters, which includes cascaded integrator-comb (CIC) interpolator and decimator, direct-form FIR and transposed FIR polyphase interpolator and decimator, FIR hold and linear interpolator, and FIR polyphase sample rate converter structures
Fractional delay filters, which includes Farrow structures
Filter Design HDL Coder can generate HDL code from cascaded multirate and discrete-time filters. Each of these single-rate and multirate filter structures supports fixed-point and floating-point (double precision) realizations. In addition, the FIR structures support unsigned fixed-point coefficients.
When you use the Filter Design and Analysis app to generate HDL code for fixed-point filters, all VHDL and Verilog output files are generated at the end of a dialog session. If the filter design requires a VHDL package, Filter Design HDL Coder also generates a package file. If you use the command line, the filter and test bench HDL files are generated separately.
Filter Design HDL Coder generates filter and test bench HDL code for a quantized filter based on an option setting or on property name and property value pairs. These settings let you:
All properties have default settings. You can customize the HDL output by adjusting the settings with the Filter Design and Analysis app or the Filter Builder app. The apps let you set properties associated with:
You can simulate and test the generated HDL code using the automatically generated VHDL and Verilog test benches. A MATLAB script can be generated for cosimulation using Link for ModelSim or Link for Cadence® Incisive® software (both available separately). This script automates the direct cosimulation of your filter design and the generated code, simplifying the task of comparing and verifying the results of the generated HDL code with the original filter design. This option enables you to utilize the advanced analysis and visualization capabilities of MATLAB to test, debug, and verify the HDL implementation of your filter designs.
After quantizing the filter, you can use dialogs to invoke Filter Design HDL Coder and configure it with optimization, content, style, and test bench options for your filter application. Supported optimizations include: